The present invention relates to an integrated circuit, and more particularly, to an integrated circuit configured to control enable/disable timing of an on-die-termination (ODT) operation for impedance control in a semiconductor device to prevent malfunctions of the semiconductor device.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include a receiving circuit configured to receive external signals from an outside world through input pads and an output circuit configured to provide internal signals to an outside world through output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal increases an influence of an external noise on the signal and causes the signal reflectance to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion in output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in decision of an input level.
In order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT circuit, near an input pad inside an IC chip.
FIG. 1 is a block diagram of a typical ODT circuit and a typical ODT control circuit provided to a DDR2 semiconductor memory device.
The ODT control circuit includes an ODT buffer 110, a setup/hold delay 120, a shift register 130, and a controller 140 to control the ODT circuit 150.
The ODT buffer 110 buffers an on/off control signal ODT received from an external controller to enable/disable ODT operations.
The setup/hold delay 120 delays the buffered on/off control signal ODTI by a predetermined delay time to secure a setup/hold margin.
The shift register 130 delays the delayed on/off control signal ODT_SH received from the setup/hold delay 120 in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3. Logic levels of the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are fixed to a logic high level in a power-down mode, whereas they toggle in the non-power-down mode. Accordingly, the shift register 130 delays the delayed on/off control signal ODT_SH only in a non-power mode.
The shift register 130 also receives termination resistance information signals ODT0, ODT1 and ODT2 from an extended mode register set (EMRS) to determine termination resistance of the ODT circuit 150 according to which signals among the termination resistance information signals ODT0, ODT1 and ODT2 are activated. For example, the termination resistance of the ODT circuit 150 is 150Ω when the termination resistance information signal ODT0 is activated, 75Ω when the termination resistance information signals ODT0 and ODT1 are activated, and 50Ω when all the termination resistance information signals ODT0, ODT1 and ODT2 are activated. The shift register 130 delays the delayed on/off control signal ODT_SH in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3, and outputs signals selected among signals ODTOUT0, ODTOUT1 and ODTOUT2 according to the activated signals among the termination resistance information signals ODT0, ODT1 and ODT2. Here, output timing of the signals ODTOUT0, ODTOUT1 and ODTOUT2 depends on the timing of the delayed on/off control signal ODT_SH. Which signal among the signals ODTOUT0, ODTOUT1 and ODTOUT2 is activated depends on which signal among the termination resistance information signals ODT0, ODT1 and ODT2 is input.
The controller 140 decodes the signals ODTOUT0, ODTOUT1 and ODTOUT2 received from the shift register 130 to activate at least one of signals SW0_UP, SW1_UP, SW2_UP, SW0_DN, SW1_DN and SW2_DN, thereby enabling/disabling resistors in the ODT circuit 150.
The circuit 160 shown at the left side of FIG. 1 receives the termination resistance information signals ODT0, ODT1 and ODT2. If at least one signal among the termination resistance information signals ODT0, ODT1 and ODT2 is activated, circuit 160 activates a signal ODTENB, thereby enabling the ODT buffer 110 and the shift register 130.
In summary, timing for enabling/disabling the ODT circuit 150 is determined by a delay time of the on/off control signal ODT. The delay time is determined by transferring the on/off control signals ODT from an external controller to the shift resistor 130 via the ODT buffer 110 and the setup/hold delay 120. In addition, the resistance of the ODT circuit 150 is determined by the termination resistance information signals ODT0, ODT1 and ODT2 activated by the EMRS. More detailed description of the operation of the ODT control circuit will be described later with reference to FIG. 4.
FIG. 2 is a circuit diagram of the ODT circuit 150 of FIG. 1.
Referring to FIG. 2, the ODT circuit 150 includes a plurality of resistors 151 to 156 for terminating an input/output node DQ in a pull-up direction or in a pull-down direction. The resistors 151 to 156 are turned on/off in response to signals SW0_UP, SW0_DN, SW1_UP, SW1_DN, SW2_UP and SW2_DN received from the controller 140.
For example, when the termination resistance is set to 150, the resistors 151 and 152 are turned on in response to the signals SW0_UP and SW0_DN to terminate the input/output node DQ with a resistance of 150. Similarly, when the termination resistance is set to 75, the resistors 151, 152, 153 and 154 are turned on, and when the termination resistance is set to 50, all the resistors 151, 152, 153, 154, 155 and 156 are turned on.
FIG. 3 is a circuit diagram of a shift register 130 shown in FIG. 1.
Referring to FIG. 3, the shift register 130 includes pass gates PG1, PG2, PG3, PG4 and PG5 which are turned on/off in response to an internal clock CK0 and shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3. Here, the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3 with different phases are generated by the output clocks FCLKDLL and RCLKDLL of the DLL.
In a non-power-down mode (i.e., when the clock enable signal CKE has a logic high level), if at least one of the termination resistance information signals ODT0, ODT1 and ODT2 are activated, the signal ODTENB is activated to a logic low level. Then, the shift register 130 becomes able to receive the delayed on/off control signal ODT_SH. While the internal clock CK0 is at a logic high level, the delayed on/off control signal ODT_SH is transferred to a node ND. Thereafter, the delayed on/off control signal ODT_SH is transferred further sequentially in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2, FCLKDLL3. Then, a NAND operation is performed on a signal ODTOND before the pass gate PG5 and a signal ODTOFFD after the pass gate PG5 to activate a shifted on/off control signal ODTS.
Then, NAND operations are performed on the shifted on/off control signal ODTS and the termination resistance information signals ODT0, ODT1 and ODT2 received from the EMRS to activate signals ODTOUT0, ODTOUT1 and ODTOUT2, respectively. Accordingly, the signals ODTOUT0, ODTOUT1 and ODTOUT2 have information about resistances according to the termination resistance information signals ODT0, ODT1 and ODT2, respectively, as well as information about enable/disable timing of an ODT operation according to the delayed on/off control signal ODTS.
In a power-down mode (i.e., when the clock enable signal CKE has a logic low level), logic levels of the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are all fixed to a logic high level to reduce current consumption. Accordingly, the pass gates PG2, PG3, PG4 and PG5 are all turned on, and thus the delayed on/off control signal ODT_SH passes through the shift register 130 without being shifted in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3.
FIG. 4 is a timing diagram illustrating operations of the typical ODT control circuit (shown in FIGS. 1 and 3) in the non-power-down mode and the power-down mode.
To begin with, the non-power-down mode when the clock enable signal CKE has a logic high level will be described. For convenience of explanation, the case where only the signal ODT0 among the termination resistance information signals ODT0, ODT1 and ODT2 is activated, i.e., the case where the termination resistance is set to 150Ω by EMRS will be described.
If the termination resistance information signal ODT0 is activated, the signal ODTENB is activated to a logic low level by the circuit 160. Then, the ODT buffer 110 and the shift register 130 are enabled. The on/off control signal ODT_SH is input from the external controller and then pass through the ODT buffer 110 and the setup/hold delay 120 to be output to the shift register 130 as a delayed on/off control signal ODT_SH. In the shift register 130, the delayed on/off control signal ODT_SH passes through the pass gate PG1 in response to the internal clock CLK0, and then sequentially transferred to the node NC and to the node ND. Thereafter, the delayed on/off control signal ODT_SH sequentially transferred further to the node NF, to the node NH and then to the node NI, in response to the RCLKDLL0, FCLKDLL1 and RCLKDLL2, respectively. The signal ODTOND before the pass gate PG5 which is turned on/off in response to the shift signal FCLKDLL3 and the signal ODTOFFD after the pass gate PG5 pass through respective delays. A NAND operation is performed on the signals ODTOND and ODTOFD to activate a shifted on/off control signal ODTS.
Then, a NAND operation is performed on the shifted on/off control signal ODTS and the termination resistance information signal ODT0 activated by the EMRS to activate the signal ODTOUT0. Accordingly, the signal ODTOUT0 has information about resistance according to the termination resistance information signals ODT0, ODT1 and ODT2 as well as information about enable/disable timing of the ODT operation according to the shifted on/off control signal ODTS.
In the power-down mode when the clock enable signal CKE has a logic low level, the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 are all fixed to a logic high level to reduce current consumption. Accordingly, the delayed on/off control signal ODT_SH passes through the shift register 130 without being delayed in synchronization with the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3. Therefore, the signal ODTOUT0 is activated and deactivated without being delayed sufficiently.
As described above, since delay of the delayed on/off control signal in response to the shift clocks RCLKDLL0, FCLKDLL1, RCLKDLL2 and FCLKDLL3 does not take place in the power-down mode, enable/disable timing of the ODT operation in the power-down mode is advanced more than in the non-power-down mode. Therefore, during the operation of a memory device in one slot (for example, in a PC, a DRAM installed in one memory slot among a plurality of memory slots), ODT operation of a memory device in a power-down mode in another slot may be performed amiss, causing a failure.